The present invention relates to a method for efficiently routing interconnects in a semiconductor integrated circuit device. In particular, the present invention provides an improved technique and structure for interconnect routing in an integrated circuit.
In a typical integrated circuit device, the surface area of the device is occupied predominantly by conductive interconnects. In fact, a typical application specific integrated circuit (ASIC) commonly relies upon a substantial quantity of conductive traces to form interconnects therein. As integrated circuits are developed to be denser and larger, it is necessary for chip designers to become increasingly aware of both the static and dynamic properties of the conductive interconnects employed in the particular circuit. Both static and dynamic properties depend upon properties of the conductor, including material type, resistance, capacitance, layout, and cell design, among others. Depending upon the particular design, such properties affect switching speed, electromigration, power dissipation, design and process compatibility, and the like, ultimately impacting reliability.
Common interconnect materials for integrated circuits include aluminum, heavily doped polycrystalline silicon, and heavily doped single-crystal silicon. Other materials for interconnects can also comprise gold, tungsten, silicides, refractory metals, or the like. The specific interconnect employed in an application depends upon a variety of factors, including reliability, stability, conductivity, compatibility with high temperature processing, among others.
Resistance of a uniform trace or interconnect depends upon material composition, width, thickness, and length. Generally, the relationship is shown as EQU R=.rho.(L/TW)
where R is the resistance, .rho. is the resistivity of the material, L is the length, T is the thickness, and W is the width. For aluminum, heavily doped polycrystalline silicon, and heavily doped single-crystal silicon, sheet resistances are about 0.04, 40, and 20 .OMEGA./.quadrature., respectively. Since the resistivity of aluminum is substantially less than the resistivity of the other interconnect materials, aluminum is generally utilized in forming lines for particular ASIC applications.
Interconnect paths made from heavily doped single-crystal silicon and heavily doped polysilicon become more resistive with increasing temperature. To decrease resistivity, silicides are typically deposited over such interconnects having higher resistances. These interconnects are sandwiches made from refractory metal silicides overlaid on either polysilicon or single-crystal silicon with no insulator in between. The combination produces a much lower sheet resistance in a given thickness than polysilicon or single-crystal silicon by itself. However, as devices have been increasingly miniaturized, silicide layers are less effective since the contact resistance between the silicide and the underlying layer predominate. Higher current densities also increase the temperature of the interconnects and therefore the resistance. Such increase in resistance further elevates the temperature and resistance of the interconnect. Moreover, the use of a silicide also increases processing difficulties and resulting costs of the integrated circuit.
As with most metals, the resistivity of aluminum also increases at higher temperatures. Such increase in resistivity occurs predominately as a result of the increase in the number of collisions of the conduction electrons with lattice phonons. Higher current densities also generally increase the temperature of aluminum and thus increase resistance which further increases temperature and resistance. As a consequence there is an increased danger of thermally induced runaway.
In an integrated circuit, higher current densities and temperatures promote the detrimental effects of electromigration. Electromigration generally refers to the transport of mass in metals when stressed to high current densities. As direct current passes through thin metal conductors in integrated circuits, high current densities may pile up metal in some regions causing a "short." High current densities may also void metal formation in other regions causing metal conductors to "open." Either problem creates detrimental effects on the performance of the device. Accordingly, current densities for typical aluminum interconnects must be kept below about 1 mA/.mu.m.sup.2. Such current densities reduce the possibility of electromigration. However, as line widths become increasingly smaller, such current densities are often difficult to consistently achieve with present grid like interconnect structures.
FIG. 1 illustrates a top view of a typical power grid gate array structure 10 (not to scale) for an integrated circuit. The power grid structure includes a V.sub.DD power pad 11, power ring 13, and V.sub.DD power grid 15 forming an interconnect. The power grid interconnection is generally made of aluminum. Aluminum typically includes a few percent of silicon and possibly copper. Silicon is alloyed with aluminum to prevent the aluminum from penetrating into the silicon substrate. Copper reduces the effect of electromigration at high currents and temperatures. The aluminum may be fabricated onto the substrate by techniques, including sputtering, masking, etching, and the like. The V.sub.DD power grid 15 further includes horizontal lines 19 and vertical lines 21. In the prior art, both the horizontal 19 and vertical lines 21 have the same relative width, thickness, pitch (spacing between adjacent lines), and density (1/spacing between adjacent lines) through the entire integrated circuit, respectively. (The vertical line numbering from left to right is for purposes which will be apparent in the subsequent text.) Lines for the typical grid structure include both V.sub.SS and V.sub.DD interconnect lines. V.sub.SS and V.sub.DD lines are typically referred to as the ground line and the power line, respectively, or generally the power lines. Metallization comprising V.sub.SS lines 24 (horizontal 27 and vertical 28), V.sub.SS ground pad 25, and V.sub.SS ground ring 26 are shown by the dashed lines. The V.sub.DD and V.sub.SS pads are typically referred to as the power and ground pads, respectively, or generally the power pads. The power lines distribute current to a plurality of cells 23 on the substrate in regions bounded by vertical lines 21 and horizontal lines 19. Each cell represents active devices including at least a MOSFET, CMOSFET, BiCMOS device, bipolar transistor, or the like.
FIG. 2 is a top view of an interconnect for gate array structure 30 with wider but fewer vertical power lines 33 than the power grid gate array structure of FIG. 1. Like the previous structure, gate array structure 30 includes a V.sub.SS ground pad, V.sub.SS horizontal lines, V.sub.SS vertical lines, V.sub.SS ground ring, V.sub.DD power ring, V.sub.DD power pad, and V.sub.DD horizontal power lines. As shown, the V.sub.SS structures are represented by the dashed lines (not to scale). However, such gate array structure relies on wider but fewer vertical power lines than the structure of FIG. 1 to decrease the current density therein. The width (W) of the vertical power line for gate array structure 30 is substantially greater than the width of the vertical power line for a comparable structure such as the power grid gate array structure of FIG. 1. However, gate array structure 30 generally uses more metal for V.sub.SS and V.sub.DD lines than desired. Accordingly, the wider vertical power lines occupy more die surface area than desired, thereby creating an inefficient use of die surface area.
With increasingly smaller line widths, the power grid structures of FIGS. 1 and 2 are inherently problematic. If a line is designed too small, the line fails to effectively transfer current therein. Specifically, high current density creates electromigration effects. Electromigration can lead to a "short" or an "open" in the interconnect structure. Alternatively, if a line is over designed, redundant metallization takes up precious die surface area which can otherwise occupy active areas. As integrated circuits become denser, effective use of die area becomes more important.
FIG. 3 illustrates current flow (I) near a top region of each line plotted against line number (n) for the structure of FIG. 1. More current flows through power lines which are geometrically closer to the power pad because of lower accumulated total resistance and the cumulative effect of a greater number of potential current sinks. As the distance between the power line and the power pad increases, the amount of current flowing through the power line decreases. The current flowing through the fifth power line 5 being connected through the shortest path to V.sub.DD is greater than the current flowing through power lines 4 to 1 or 6 to 9. The larger current flowing through power line 5 leads to higher temperatures and therefore provokes problems including electromigration, slower switching speeds, higher power consumption, and others. Less current flowing through lines 1 and 9 may indicate that such lines were over designed and therefore occupy more die area than necessary. A similar current distribution is also present in the structure of FIG. 2.
A specific example of a power grid structure 60 for a gate array which was actually simulated is illustrated by the top view of an integrated circuit of FIG. 4. The power grid structure includes a power ring 62, V.sub.DD power pad 65, vertical power lines 64, and horizontal power lines 67. A V.sub.SS ground pad 61 and V.sub.SS lines 69 are also shown as represented by the dashed lines (not to scale). A plurality of active cells 68 are in the regions between adjacent power lines. Power grid structure 60 comprises "n" vertical power lines numbered from the left side of the integrated circuit and "m" horizontal power lines numbered from the top of the integrated circuit. For the device of FIG. 4, n and m are equal to 48 and 256, respectively. Both horizontal and vertical power lines each have a width of about 2.1 .mu.m (.mu.) and the power ring has a width of about 97.3.mu.. The thickness of each power line is about 1.0.mu. and the lines also comprise aluminum. The integrated circuit also has a length (L) of about 9690.mu. and a width (W) of about 9702.mu.. Each cell has a width of 10.5.mu. and a length of 30.mu., and includes two p-channel MOS transistors and two n-channel MOS transistors. To exercise the device for simulation, a current source at about 128 mA was applied to the V.sub.DD power pad. Current through the integrated circuit is assumed to be uniformly dissipated therein. Actual measured values of current density near a top region of each line confirm higher current densities are localized near the V.sub.DD power pad, as represented in Table
TABLE 1 ______________________________________ VERTICAL LINE NUMBER CURRENT DENSITY (mA/.mu..sup.2) ______________________________________ 1 0.24 2 0.18 3 0.20 4 0.22 5 0.24 6 0.27 7 0.30 8 0.33 9 0.36 10 0.40 11 0.45 12 0.50 13 0.55 14 0.62 15 0.69 16 0.78 17 0.88 18 0.98 19 1.10 20 1.24 21 1.41 22 1.64 23 2.00 24 2.86 25 2.86 ______________________________________
Specifically, the highest current density existed at vertical power lines 24 and 25. These two power lines are directly adjacent to the power pad as shown. Vertical power lines 24 and 25 each have a current density of 2.86 mA/.mu..sup.2. Such current density is substantially greater than the upper value of 1 mA/.mu..sup.2 for an interconnect comprising aluminum. Such upper value is the current density value at which the effects of electromigration begin.
To further illustrate the non-uniform distribution of current, current density as a function of vertical power line distribution for the integrated circuit of FIG. 4 is illustrated by FIG. 5. The horizontal axis represents line numbering (n) and the vertical axis represents current density near a top region of each line (mA/.mu..sup.2). As shown, the current density increases from about 0.20 mA/.mu..sup.2 at the edge of the die to about 2.86 mA/.mu..sup.2 for the power lines directly adjacent to the power pad. As for power lines 1-3 which are near an edge, the current density is substantially less than the design criteria of 1 mA/.mu..sup.2. Thus, the power lines near the edge use more die area than desired, thereby creating an inefficient use of die surface area. The power lines near the power pad have a current density substantially greater than the upper value of 1 mA/.mu..sup.2 for an aluminum interconnect, thereby requiring more metallization to reduce current density and electromigration problems. Accordingly, the integrated circuit illustrated suffers from non-uniform current densities which aggravate electromigration effects and impair efficient use of die surface area.
As illustrated in FIG. 5, current is not uniformly distributed among power lines of a typical integrated circuit having a grid like power interconnect structure. The combination of substantially even spacing between the power lines and uniform power line width, thickness, and length cause higher current densities near particular regions. Such regions include power pads and power bus lines, among others. Higher current densities also increase the temperature at such regions. Higher temperatures coupled with high current densities may provoke the detrimental effects of electromigration as well as degrade device performance. The problems described herein exist in integrated devices such as application specific integrated circuits (ASICS), custom integrated circuits, standard products including at least microprocessors (MICROS), gate arrays, programmable devices, and the like. Such integrated devices may employ technology including metal oxide silicon field effect transistors (MOSFET), complementary metal oxide silicon field effect transistors (CMOSFET), bipolar complementary metal oxide silicon field effect transistors (BiCMOS), bipolar transistors (bipolar), among others.